Traditional approaches that rely solely on simulation are far too time consuming to solve the bottleneck of design verification and hence risky for today's complex circuits. Simulating for days , weeks or months to determine if a design revision caused a functional problem is unacceptable. The development of test cases also requires a huge amount of works but is still far from approaching exhaustiveness in the validation of a model against its specification. Formal Verification and Prototyping represent alternatives which can be an order of magnitude more efficient than software simulation.