An abstraction tool to produce automatically RTL/Logic descriptions from hierarchical mixed gate/transistor netlists. Different design styles including dynamic logic can
be recognized automatically.
Main Features
Hierarchical processing of the netlists including the ability to flatten or to black-box during abstraction.
Name preservation
Generation of flattened of hierarchical logic models.
Availability
Release 2.0 available on Sun OS, Sun Solaris, HP, DPX20 and PC
