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| LEQTM (Logic EQuivalence) |
A formal verification tool that analyzes the quality of complex logic
designs (eg. detection of functional loops, dead codes, unused objects, conflicts, ...), provides formal comparison at
different levels of abstraction (RTL/RTL, RTL/Gate, Gate/Gate) and assists in debugging logic errors. The proprietary Boolean
manipulation technique developed by METASymbiose provides LEQ
with the ability to handle large and complex design including arithmetic operators (eg. multiplier).
Main Features
- Automatic procedure to match registers/latches
- Automatic hierarchical comparison
- Definition of constraints for comparison : Assignment of constant values, definition of equivalence or exclusivity to input nodes, ...
- Ability to handle DC in FSM coding
- Original debugging procedure leading to convergence towards errors location
- ... etc.
Availability
- Release 2.5 available on Sun OS, Sun Solaris, HP, DPX20 and PC
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